1. Field of the Invention
The present invention relates to substrate processing, and more particularly to improving the substrate processing using optimized spacer procedures and subsystems.
2. Description of the Related Art
Current low cost products use a bulk silicon technology. As the transistor continues to shrink, the impact of the channel depth is becoming critical (ultra-shallow source/drain extensions). As the SOI (silicon-on-insulator) film shrinks, smaller variations in the spacer thickness and thickness of the SOI film can affect the transistor's performance. When spacer-etch procedures are not controlled, the removal of the spacer material near the gate affects the electrical performance.
Current high performance microprocessors from device manufacturers, such as International Business Machines (IBM) and Advanced Micro Devices (AMD), use PD SOI (partially depleted SOI film having a threshold voltage 0.2 volts. PD SOI film thicknesses are around 50 nm while the spacer reduction amount can be a large percentage (e.g., 10%) of the total spacer thickness. Future generations of SOI films are labeled FD SOI (fully depleted SOI film having a threshold voltage 0.08 volts and a thickness of about 25 nm). Currently theses films are not in production due to limitations in thickness control uniformity and defects. Channel mobility degrades with decreasing SOI thickness. With thinner SOI film, the control of the spacer sidewall thickness becomes more critical.